At the same time, CPU performance is going to up by more than 2x, CPU communications channels like HT and QPI have more than doubled, memory performance has gone up more than 2x and SAS performance has likely more than doubled. Here is the SAS Roadmap. Note that 3.0 Gbit overlapped PCIe 1.0, and PCIe 2.0 and 6 Gbit will overlap PCIe 2.0 and 3.0, supposedly soon to arrive. We will get 12 Gbit in 2013.
6 Gbit=768 MB/sec is about 1.5 PCIe 2.0 lanes per SAS lane. 12 Gbit is of course also about 1.5 PCIe 3.0 lanes. The SAS roadmap and the PCIe roadmaps and releases do not see to match very well. PCIe lanes are usually 4 and 8 now sometimes 16. Clearly SAS lanes and PCIe lanes are a major mismatch. (e.g., 4 SAS 6 Gbit lanes equal 6 PCIe lanes). Besides the mismatch on performance with SAS and PCIe, I think performance is lagging, but that is another topic. We will get 24 Gbit SAS and be stuck on PCIe 4 at 2 GB/sec per lane and still have the mismatch with 3 GB/sec per SAS lane. This mismatch, given the number of PCIe lanes most vendors provide and the number of SAS lanes most vendors provide, means that you either waste PCIe lanes to ensure the SAS card runs at rate or waste SAS lanes if you oversubscribe the PCIe bus. This does not make for good balance, and maybe the PCI-SIG should think about matching the SAS performance rather than going down a separate patch.
Many believe that long-term SAS will be the dominant storage connectivity market space. It is about time the PCI-SIG get in lock step with one of its biggest users.