A flash controller chip manages the data stored on flash memory and communicates with connected devices. Current flash controller technology is improving very rapidly. To a large extent these improvements are possible because falling costs have made it practical to use increasingly powerful controller chips that can run more sophisticated firmware faster.
In other words, improvements in controller technology more than offset the inferior speed and durability characteristics of MLC. "That means that today's SSDs are more reliable and have better wear than ever. Today's MLC is better than yesterday's SLC," he explains.
This progress is continuing, which has important implications for overcoming the main drawback of triple-cell technology: TLC is more prone to errors and thus needs much better error correction technology than was the case with MLC or SLC.
Such error correction technology is available, in the form of a powerful but computationally complex error correction algorithm called Low Density Parity Check (LDPC). (LDPC was originally invented in the 1960s, but it required more processing power than was available at the time, so it was largely ignored then.)
"LDPC requires a far higher gate count in the controller hardware, so implementing LDPC may add 30 percent to the cost of the controller," says Handy. But thanks to falling controller hardware prices, it is now becoming practical to implement LDPC in controller silicon, and some manufacturers are now starting to use it in their controllers.
As a result of this type of hardware innovation, TLC is becoming increasingly attractive, and it is likely to make up 50 percent of total flash production by the end of 2015, according to research from DRAMeXchange. "I do believe that eventually everything will be using TLC," says Handy.
The other major flash innovation on the horizon is the development of 3D flash: memory that is built in layers stacked on top of each other with vertically-oriented cells. Current technology involves 2D planar flash, which is made in a single layer with cells that are oriented horizontally.
"3D flash is on all the manufacturers' roadmaps. That's because they have realized that they can no longer increase capacity by shrinking the size of the cells in the way that they have been doing," says Handy.
Because 3D flash allows for many more cells in a given surface area (because they are aligned vertically and stacked on top of each other), overall capacity can be increased while actually using a larger cell size. Typical planar flash cells are made using a 15nm process, while 3D cells are currently made using a 45nm process. This larger size has the added benefit of making 3D flash much less subject to errors due to interference from neighbors and therefore more reliable than smaller cells. Samsung has already started producing SSDs that use 32-layer 3D TLC to produce 1TB drives, and in March Toshiba announced that it is developing 48-layer 3D flash using MLC. Improved fabrication techniques are likely to enable manufacturers to make 3D flash (using MLC and TLC) with even more layers in the near future.
"We don't know what the limit to the number of layers is yet, but today it's thought that it is about a hundred," says Handy.
From an economic point of view it's interesting to note that the prices per gigabyte of both HDDs and SSDs have been falling at about the same rate for at least the last seven years. Flash storage has remained about twenty times more expensive per gigabyte than spinning disk storage during that time, Handy says.
The good news for enterprises with rapidly expanding storage requirements is that improvements in cell technology, enhanced controllers and 3D flash mean that flash storage costs are set to continue falling rapidly in line with HDDs for the foreseeable future.
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