Ultra160 SCSI defines new performance level

Posted on June 01, 2000


Three key features differentiate the new standard from its predecessors.

By Joe Lepine

Driven by escalating server and workstation requirements, SCSI vendors have recently brought to market the first products compliant with the new Ultra160 SCSI standard. Offering up to 160MBps, or double the performance of the established Ultra2 SCSI interface, Ultra160 devices will play a crucial role in the evolution of high-performance storage subsystems.

However, Ultra160 SCSI is a relatively new specification, and, as such, it raises a number of questions. What attributes differentiate the latest SCSI implementation from its predecessors? How did developers push the specification to its new level of performance? And how will the new capabilities in Ultra160 SCSI impact compatibility issues?

There are three distinctly new features in Ultra160 SCSI: double-edge clocking, cyclical redundancy checking, and domain validation.

Double-edge clocking

By transitioning on sampling data on both edges of the data strobe, the bus can transfer twice the amount of data while retaining the same electrical characteristics. Double-edge clocking, or double-transition clocking, is largely responsible for Ultra160 SCSI's new performance capabilities. It allows twice the data transfer rate of Ultra2 SCSI (80MBps) implementations, without additional internal clocking. At the same time, the new specification is backward compatible with existing Ultra2 and legacy SCSI devices.

Cyclical redundancy checking

However, the use of double-transition clocking to push data transfer rates to 160MBps poses new signal integrity issues. To compensate for those issues, Ultra160 SCSI adds a second new feature: cyclical redundancy checking (CRC). While earlier versions of SCSI used parity checking to detect transmission errors, CRC brings a higher level of error detection capability that is more effective for higher-speed data transfers.

Used extensively in Fast Ethernet, FDDI, and Fibre Channel technologies, CRC provides a more comprehensive error-detection technique by performing a cyclic algorithm on each block of data to be transmitted. The sending device then inserts the results of its computation into each data block. Once the data block is transmitted, the receiving device applies the same algorithm on each block of data it receives, and then compares its results with the received CRC code. Depending on the outcome, it sends either a positive or negative acknowledgment that the data was transferred correctly. The CRC technology used in Ultra160 SCSI is capable of detecting all single-bit and double-bit errors, all odd number of errors, and all burst errors up to 32-bits long.

By checking all transferred data instead of a single byte, CRC offers a significant improvement in data reliability over previous versions of SCSI. It provides an extra layer of data protection for marginal cable plants and external devices, and ensures data protection during hot plugging. Additionally, by introducing this error-detection technology to the standard, CRC lays the foundation for future, higher-performance versions of SCSI.

Domain validation

Domain validation, the third new feature in Ultra160 SCSI, plays a critical role in verifying that a system can transfer data at Ultra160 data rates. Until now, the host controller on a SCSI board has determined what data transfer rate it will use with each connected device through an INQUIRY command. That approach presented one major liability: there was no guarantee that the connection could support the negotiated data rate. Without this assurance of compatibility, problems could occur, rendering the device inaccessible.

Domain validation eliminates this potential liability by verifying that the SCSI connection can transfer data at the negotiated rate. Once a transfer rate is negotiated, it is checked at that rate. If errors are detected, the controller automatically steps down the rate and/or width until a connection is established that is error free. This approach increases uptime and significantly reduces installation problems, support calls, and cost of ownership.

The ANSI T10 SPI-3 specification defines two levels of domain validation for Ultra160 SCSI. Controllers perform Level 1, or basic domain validation, by issuing two INQUIRY commands with the timing parameters set to asynchronous and narrow. The returned data is then stored for later use.

Next, the controller issues a second INQUIRY command with the period and width set to the desired transfer rate. Data from the second command is then compared to data received from the first. If the data does not match, then the initiator automatically falls back to a lower speed and width and tries the INQUIRY again. If the data does match, then the initiating controller and the target communicate at the negotiated speed. This first level of domain validation is useful in finding problems with cabling, expanders, faulty transceivers, and improper termination.

The second level specified in SPI-3 specification is Level 2, or enhanced domain validation. This function goes beyond Level 1 by adding the ability to send and receive patterns of data. To perform Level 2 domain validation, a controller issues multiple READ/WRITE BUFFER commands and compares the data sent to the data received.

Initially, the controller issues a WRITE BUFFER with a desired data pattern. Next, a READ BUFFER is sent to the same buffer. The data of the READ BUFFER is then compared to the data sent during the WRITE BUFFER. If there is no match, the initiating controller renegotiates the data rate down. When there is a match, the process is repeated with another data pattern. Several data patterns can be used to check different types of potential failures. This capability is useful in finding problems such as crosstalk, system noise, weak or strong transceivers, improper termination, incorrect device spacing, and cables with the wrong impedance.

While the first two levels meet the requirements for the Ultra160 SCSI specification, domain validation can be taken one step further by implementing margined domain validation. With signal edge rates running between 1 and 4 nanoseconds, and bandwidth in the gigahertz range, the physical demands of SCSI board design are extremely high. At this level, the slightest variation in design can have a major impact on impedance and bus skew, and it can potentially undermine signal integrity.

Margined domain validation gives system designers information on the margin of safety that exists on the bus. This approach uses the same WRITE/READ BUFFER tests used in enhanced domain validation. But by altering the electrical characteristics of the SCSI signals at the same time, margined domain validation gives designers the ability to quantify and verify the degree of tolerance their designs can handle. Vendors can also verify the marginal characteristics of the bus by varying the clock signal timing characteristics.

Ultra160 SCSI marks a significant step forward in I/O technology, and enables the interface to keep up with the escalating performance capabilities of microprocessors, disk drives, and system buses. The new standard provides a dramatic increase in data transfer rates, while retaining compatibility with legacy SCSI systems. The key to achieving this high level of performance is the implementation of Ultra160's three new design features: double-transition clocking, CRC, and domain validation.

Joe Lepine is product marketing manager at LSI Logic Corp., in Milpitas, CA. www. lsilogic.com. LSI is a member of the SCSI Trade Association: www.scsita.org.

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