PCIe 4.0, Not a Good Plan

I just saw that the PCI-SIG (PCI Special Interest Group) announced PCIe 4.0 will double PCIe 3.0 performance and--sit down for the next part--it will arrive in 2015 or 2016. Given how late PCIe 3.0 was, I would say that 2016 would be optimistic at best. So from 2004 with PCIe 1.0 to 2016, we will go from 250 MB/sec per lane to 2 GB/sec per lane or a factor of 8x in 12 years. Big deal.

Moore's Law is certainly not in play for PCIe. During that time, everything else has increased far more than 8x. In 2004, we had LTO-2 at 35 MB/sec; today, we have tape drives well over 240 MB/sec. Surely, we will have another generation faster. We have faster memory, faster CPUs faster communication with 10 GbE and 40 GbE coming (100 GbE depends on PCIe 3.0). The only thing in the stack that is not that much faster is spinning disk, but we of course have flash SSDs that are far more than 8x faster.

The message from the PCI-SIG is basically saying, "wow, we are doing just a great job getting you 2x performance by 2015 or 2016." I see this as a major problem. PCIe is required for all communications, and it just is not fast enough as things scale out, whether for storage or for network communication. It is time for the PCI-SIG to realize we need something much faster. 2x every four years is not fast enough, and we are already pretty far behind since PCIe 3.0 was so late that it is not even here yet.

Labels: Moore's Law,PCIe,Storage

posted by: Henry Newman

Henry Newman, InfoStor Blogger
by Henry Newman
InfoStor Blogger

Henry Newman is CEO and CTO of Instrumental Inc. and has worked in HPC and large storage environments for 29 years. The outspoken Mr. Newman initially went to school to become a diplomat, but was firmly told during his first year that he might be better suited for a career that didn't require diplomatic skills. Diplomacy's loss was HPC's gain.

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